This invention relates to a multi-CPU system for industrial use, and more particularly to a multi-CPU system which is suitable for mounting operation systems (OSs) different from each other in a master CPU block and in a slave CPU block, respectively.
Now, a conventional multi-CPU system will be described with reference to FIG. 7.
The conventional multi-CPU system includes a CPU 3 which has a ROM 4 and a RAM 5 connected to the RAM 4, to thereby constitute a master CPU block 2. The master CPU block 2 has a storage means 6, an input unit 7 such as a key board, a mouse or the like, and a monitor 8 connected thereto. The master CPU block 2 and the units connected directly thereto are operated by a user and referred to as a master-side section 1 in the lump herein. The CPU 3 is also connected through a bus 9 to slave blocks 15 and 21. The slave CPU blocks 15 and 21 include CPUs 11 and 17, respectively.
The CPU 11 has a communication means 10, a ROM 12, a RAM 13 and a measure/control function section 14 connected thereto. Likewise, the CPU 17 has a communication means 16, a ROM 18, a RAM 19 and a measure/control function section 20 connected thereto. The CPU 3 of the mater CPU block 2 is constructed so as to access to the communication means 10 and 16 of the slave CPU blocks 15 and 21. The slave CPU blocks 15 and 21 thus constructed are operated according to programs stored in the ROMs 12 and 18, respectively.
The measure/control function sections 14 and 20 are connected in common to an equipment which is to be subject to measure and control (hereinafter referred to as "measured/controlled equipment") designated at reference numeral 30. The measured/controlled equipment 30 is controlled by the CPUs 11 and 17. The slave CPU blocks 15 and 21 connected to the measured/controlled equipment 30 is referred to as a slave-side section 29 in the lump herein. The measure/control function sections 14 and 20 each include functions such as, for example, a contact input and output function, an analog/digital converter (hereinafter referred to "ADC"), a digital/analog converter (hereinafter referred to as "DAC") and the like.
Additional slave CPU blocks constructed in substantially the same manner as the slave CPU blocks 15 and 21 are arranged, to thereby ultimately provide the multi-CPU system.
In the conventional multi-CPU system thus constructed, the programs for the CPUs 11 and 17 of the slave CPU blocks 15 and 21 are stored in the ROMs 12 and 18, respectively. Thus, when it is required to change the programs in order to change a function of the slave CPU blocks 15 and 21, the ROMs 12 and 18 must be changed. However, a change of the ROMs is highly troublesome. For example, in-situ replacement of a built-in ROM of an equipment is highly troublesome, leading to an increase in maintenance cost.
Also, the conventional multi-CPU system is so constructed that the slave CPU blocks 15 and 21 are respectively operated according to the programs different from each other. This requires an additional program for adjusting a timing of operation of any one of the slave CPU blocks 15 and 21 associated with operation of the other slave CPU block. Also, such adjustment must be carried out by the CPU 3 of the master CPU block 2.
Now, this will be further described with reference to FIG. 7.
Control of the measured/controlled equipment 30 connected to the measure/control function blocks 14 and 20 requires in addition to the programs respectively stored in the ROMs 12 and 18 of the slave CPU blocks 15 and 21, an adjustment program for adjusting a timing of operation of the programs. Thus, the programs stored in the ROMs 12 and 18 and the adjustment program of the CPU 3 of the master-side section 1 cooperate with each other to constitute a control program for controlling the measured/controlled equipment 30.
Now, operation of the DAC by the slave CPU block 15 and operation of the ADC by the slave CPU block 21 for exchange of a signal through the measured/controlled equipment 30 will be described.
First of all, the slave CPU block 15 operates the DAC to feed an analog signal to the controlled/measured equipment 30, so that the measured/controlled equipment 30 may carry out some operation. Then, the measured/controlled equipment 30 feeds results of the operation in the form of an analog signal to the slave CPU block 21, so that the slave CPU block 21 digitalizes the signal and outputs it to the CPU 3. In such a signal exchange, the programs for the CPUs 11 and 17 are insufficient to permit a timing of operation between the CPUs 11 and 17 to be adjusted, because the CPUs 11 and 17 are operated by means of the programs different from each other. Thus, control of a timing at which the CPU 17 takes in a signal of the DAC is carried out through the communication means 16 by means of the CPU 3 of the master-side section 1.
However, in general, the CPUs 11 and 17 of the slave-side section 29 each are mounted therein with an operation system (hereinafter also referred to as "OS") which exhibits real time characteristics suitable for a control system and the CPU 3 of the master-side section 1 is mounted therein with an OS which is free of any real time properties but suitable for a user interface. The OS free of real time properties which is mounted on the CPU 3 of the master-side section 1 is not suitable for adjustment of a timing of operation of each of the blocks. Thus, adjustment of an operation timing of each block by means of such an OS renders a program of the whole system complicated, to thereby cause preparation of a control program therefor to be highly troublesome or difficult.